1. Field of the Invention
The present invention relates to a resonant inverter, and more particularly to a resonant inverter exhibiting a depressed duty variation.
2. Description of the Related Art
FIG. 1 is a circuit diagram illustrating an example of a conventional resonant inverter 100. In FIG. 1 a voltage/current converter 110 includes an OP amplifier 111 and a transistor M3. Voltage/current converter 110 is connected to an external resistor RT. In operation, a reference voltage VREF is applied to a non-inverting terminal (+) of the OP amplifier 111. An inverting terminal (−) of the OP amplifier 111 and a source of the transistor M3 are connected to the external resistor RT. A current IC is drawn by the voltage/current converter 110 through the external resistor RT. A drain of the transistor M3 is connected to a current mirror 120. The current mirror 120 includes two transistors M4 and M5. The current mirror 120A outputs a mirror current Icm, proportional to a current IC. Mirror current Icm is applied to a current-controlled oscillator (CCO) 130.
The CCO 130 generates a square output clock CLK in accordance with the output from the current mirror 120. The output clock CLK is input to a dead time generator 140 which, in turn, generates a high-side input signal HIN and a low-side input signal LIN. The high-side input signal HIN is input to a high-side driver 150, whereas the low-side input signal LIN is input to a low-side driver 160. The high-side driver 150 controls a transistor M1 via the high-side input signal HIN. The low-side driver 160 controls a transistor M2 via the low-side input signal LIN. A source of the transistor M1 and a drain of the transistor M2 are connected to each other at an output node. A resonant tank 170 is connected to the output node. One of the functions of the resonant tank 170 is to be an output terminal of the resonant inverter.
FIG. 2 is a waveform diagram illustrating an operation of the resonant inverter of FIG. 1. The current IC can be expressed by the following Equation (1):
                    IC        =                  VREF          RT                                    (        1        )            
The CCO 130 outputs an output clock CLK having an output frequency determined by Icm. When the transistors M1 and M2 are simultaneously turned on, the resonant inverter may be damaged due to short-circuit current flowing through the transistors M1 and M2. The dead time generator 140 prevents the transistors M1 and M2 from turning on simultaneously by an appropriate high-side input signal HIN and low-side input signal LIN. The dead time generator 140 introduces a dead time td, during which both the high-side input signal HIN and the low-side input signal LIN assume a low level, in short, both HIN and LIN are low. An output signal OUTPUT transitions during the dead time td. When the high-side input signal HIN is high, the transistor M1 is turned on and the transistor M2 is turned off. In this state, the output signal OUTPUT is high. On the other hand, when the low-side input signal LIN is high, the transistor M1 is turned off and the transistor 2 is turned on. In this state, the output signal OUTPUT is low.
FIG. 3 is a circuit diagram to illustrate an electrostatic coupling phenomenon occurring in the resonant inverter of FIG. 1. A parasitic capacitor Cp may be formed between the output node of the resonant inverter and the node where the external resistor RT and the voltage/current converter 110 are connected. The formation of the parasitic capacitor Cp may be caused by various factors, for example, various patterns on a printed circuit board (PCB) on which the resonant inverter is formed.
A consequence of the presence of the parasitic capacitor Cp can be that the current IC flowing through the external resistor RT can be influenced by the output signal OUTPUT. As a result, the duty and output frequency of the CCO 130 can vary. Although such a phenomenon can be suppressed by reducing the capacitance of the parasitic capacitor Cp, this reduction can be difficult in practice. The influence of a current IP flowing through the parasitic capacitor Cp may also be reduced by increasing the current IC. In this case, however, the size of an oscillating capacitor (not shown) internally included in the CCO 130 may need to be increased, occupying excessive chip area.